The present invention relates to field effect transistors, and, more particularly, to a vertical double-diffused metal oxide semiconductor (VDMOS) device.
A VDMOS integrated structure includes source, body and drain regions of alternate type conductivity defined in a semiconductor electrically in series with each other. The body region is a diffused region that extends into the semiconductor while the source and drain regions are disposed near the surface of the semiconductor to define a certain length and width of a channel region in the body region. An insulated gate electrode is formed on the surface of the semiconductor, geometrically above the channel region.
In operation, by applying an appropriate voltage on the gate electrode, the type of conductivity of the diffused body region in the portion defined as the channel region, between the source and drain regions and directly underneath the gate electrode, is inverted. This forms a superficial channel in a depleted channel region.
The inverted channel allows a current flow between the source region formed inside the body region and the drain region of the device, which commonly surrounds the body region and which may be contacted on the bottom face of the semiconductor wafer. A typical VDMOS structure is described in U.S. Pat. No. 4,145,700.
The structure formed by the distinct regions of the source, body and drain of a VDMOS device in the semiconductor substrate determines the existence of either an NPN or PNP parasitic bipolar junction transistor. This depends on the respective types of conductivity of the regions of the VDMOS transistor structure.
The inevitable presence of this parasitic bipolar transistor structure is detrimental for important electrical characteristics of the VDMOS structure, and its effect must be minimized. Many ways have been proposed to reduce as much as possible the gain of such a parasitic bipolar transistor.
There are substantially two types of known techniques for reducing the gain of the parasitic bipolar transistor. A first approach short circuits the base and the emitter of the parasitic transistor with the metal that contacts and connects the source region of the VDMOS structure. A second and most commonly followed approach increases as much as possible the doping level of the base region of the parasitic transistor, represented by the body region of the VDMOS structure.
Although the latter approach is easy to implement in a normal manufacturing process for a VDMOS structure, it contrasts with the objective of maintaining a voltage threshold of the VDMOS between 1 and 5 volts. This imposes that the dopant concentration in the body region be kept between about 1016 and 1017 atoms/cm3. This is definitely insufficient to effectively lower the gain of the parasitic bipolar transistor.
These contrasting requirements and incompatibilities are generally overcome by forming a body region which is not homogeneous, but is in the form of two layers or diffused regions formed independently from one another. A first zone of the body region establishes the concentration of dopant in the superficial channel region, and thereby the turn-on threshold voltage. The other zone of the body region has a relatively higher dopant concentration to provide for a base region of the parasitic transistor with a high dopant concentration to significantly reduce its gain.
These two zones of the body region with a different dopant concentration are made by two distinct dopant implants. For instance, a dose of about 1013 atoms/cm2 is made for the implantation that determines the turn-on threshold voltage of the device. An increased implant dose of about 1015 atoms/cm2 or greater is made to increase the dopant concentration in the zone that forms the base region of the parasitic transistor.
Commonly, this differentiation of the dopant level of the body region is made possible by either using two distinct masks, or by other additional processing steps. This increases the complexity of the fabrication process. FIGS. 1a to 1e schematically illustrate the basic steps of a prior art process for realizing a so-called deep body region having an increased dopant concentration to decrease the gain of the parasitic structure.
According to this known process, through a purposely reduced aperture of a mask M1 a first implantation is carried out. Mask M1 is typically formed by a patterned layer of silicon oxide with a thickness generally between 1 to 2 mm. In the considered example, the implanted dopant B is boron. The implant is generally made at 60 to 100 KeV, with a dose generally between 5*1014 and 5*1015 atoms/cm2. This heavy implantation carried out through the relatively reduced mask aperture prevents a subsequent lateral diffusion of the implanted dopant, which may reach the channel region. This would increase the threshold voltage of the device.
A second body implantation is performed after having grown a gate oxide layer 3 on the n type epitaxial semiconductor grown over the n+ type semiconductor substrate. This is a reduced dose of boron implantation, generally between 1013 to 1014 atoms/cm2, at 80 to 100 KeV. This implantation forms the superficial p-type body region in which the channel region of the structure is established. This ensures the desired turn-on threshold voltage of the device. This second shallower body implantation takes place through an aperture defined in a polysilicon layer 4 which will form the gate electrode of the device.
As shown in FIG. 1c, the dopant implant in the two distinct steps is diffused in the semiconductor, producing the characteristic profile of the body diffusion. Thereafter, the layer of the gate oxide is removed by masking and etching steps, and the n+ type source implant is carried out as depicted in FIG. 1d. 
FIG. 1e shows the details of the structure after the deposition of an insulating dielectric layer 5, the opening of a via exposing the source contact zone, and the deposition of a metal layer 6. FIG. 1f shows the doping characteristic profile across a section of the epitaxial layer 2.
The set of FIGS. 2a-2g schematically shows another known prior art process that does not use the so-called deep body. This method includes realizing a buried body region (shallow body) having a high dopant concentration as described in U.S. Pat. No. 4,587,713.
According to this alternative technique, through the opening defined in the polysilicon layer 4, a first boron implantation of a moderate dose is carried out to ensure the desired turn-on threshold voltage of the device, as shown in FIG. 2a. This is followed by the dopant diffusion as depicted in FIG. 2b. 
Thereafter, through a second photoresist mask R, a second boron implantation is performed at relatively high kinetic energies of about 150 to 500 keV, and in a dose sufficient to form a p+ type region with a relatively high doping level at a certain depth and within the p-type body diffusion already formed. The concentration peak of this p+ type region, often referred to as shallow body, should be located beneath the future source zone. This is realized by using an appropriate implantation energy. This step is schematically illustrated in FIG. 2c. 
The fabrication process continues, similarly to the preceding case, with the masking and etching of the gate oxide layer 3 in the source zone, and with the n+ type source implant directly above the previously formed heavily doped p+ region (shallow body), as shown in FIG. 2d. FIG. 2e is a schematic cross section of the complete functional structure, and FIGS. 2f and 2g respectively show the doping characteristic profiles along a section crossing the source region and along a section not crossing the source region.
A second masking stage becomes necessary because if the high energy implant should be subjected to the annealing treatment of the body region, there would be a lateral diffusion of the dopant, and an expansion of the highly doped region reaching the region beneath the electrode 4. In other words, the expansion of the highly doped region reaches the channel region, which would undesirably alter the threshold voltage.
In order to eliminate the need for two distinct masking steps, the process described in U.S. Pat. No. 4,774,198, which is assigned to the current assignee of the present invention and which is incorporated herein by reference in its entirety, discloses the use of spacers on the patterned edges of the polysilicon. The ""198 patent also discloses the implantation of the highly doped p+ type buried region through the restricted opening using the silicon oxide spacers. This is done while reducing the kinetic energy so that the implant is sufficiently shielded by the polysilicon layer. The shielding provided by a relatively thick masking resist layer does not exist in this case.
Thereafter, the fabrication process includes the elimination of the purposely formed spacers by a selective etching to open the source areas and the successive n+ type implant. This is done according to a normal fabrication sequence of operations.
Despite the advantage of eliminating the need for a second masking operation, the limitation of the kinetic energy of the implants that may be used without negatively affecting the electrical characteristics is an important drawback that is further accentuated by the scaling down of integrated devices. The electrical characteristics are negatively effected due to the passage of dopant through the masking gate electrode layer.
A fabrication method has now been found that eliminates the need for a second masking operation while permitting a high kinetic energy implant without particular constraints due to the relatively limited shielding capacity of an already patterned polysilicon gate layer. The implant is carried out through a resist mask having an adequate shielding capacity. Furthermore, the improved method of the invention also eliminates the need for additional operations, such as forming spacers of silicon oxide.
The method according to the present invention produces a substantial reduction in the complexity of the known processes, as well as a substantial elimination of the critical limits. The present invention also reduces the occasional insufficient shielding during a high energy implant of a dopant to form a highly doped buried shallow body region. The method according to the present invention offers a wide range of choices of implanting energies, and allows for a more precise positioning of the highly doped buried body region. This positioning may be inside a lightly doped body region previously formed with an appropriate dopant level to ensure the desired threshold voltage of the device.
The fabrication method of the invention comprises forming, after having formed the properly doped diffused body region, a resist mask that defines the implantation apertures of the source region. This is prior to the formation of the highly doped buried region inside the body region previously formed by implantation and diffusion of the dopant.
Through this resist mask, a dopant of the same conductivity type of the preformed body region is implanted at a sufficiently high kinetic energy. The implantation may extend down to a certain depth from the surface of the semiconductor substrate.
Another dopant of conductivity type opposite to the conductivity of the dopant used to realize the body region is implanted through the same mask. The implantation of this other dopant is performed at a lower kinetic energy than the one used to implant the dopant of the highly doped buried body region. This implantation forms source regions geometrically above the highly doped buried body regions, that is, in a superficial zone of the body region.
In view of the fact that the diffusion of the dopant implanted in the source region typically requires an annealing process at approximately 900-1000xc2x0 C. for 10-20 minutes, or an RTA at 1100-1150xc2x0 C. for 20-40 seconds, the coping profile of the superficial body zone remains practically unaltered and the threshold voltage is unmodified.
The resist mask shields those areas sensitive to high energy implantations through a masking step that is eliminated from the flow-sheet of a standard fabrication process. Additional steps are not necessary to form dielectric spacers along the defined aperture of the source area through the polysilicon gate layer, according to the known prior art process discussed above.